In recent years, there has been an increased demand for electrical switching elements which are capable of operating at higher operating speeds and which have higher breakdown voltages. To satisfy these demands, a vertical type power MOSFET, in which current between the two main surfaces of the semiconductor substrate is controlled by a plurality of MOS structures, has been developed primarily for use as a switching element for power supplies. A conductivity modulating type MOSFET, also known as an insulated gate bipolar transistor (IGBT), has made it possible to reduce the ON resistance of the MOSFET by utilizing conductivity modulation and its use will broaden to inverter control in situations where higher break down voltages and higher electric power is required.
FIG. 2 shows a cross-sectional view of an n-type channel IGBT. In FIG. 2, there is an n.sup.- drift region 2, overlying p.sup.+ collector region 1. A p base region 3 is selectively formed on the surface of the n.sup.- drift region 2. On the surface of the p base region 3 two n.sup.+ source regions 4 are formed. Centrally formed between the two n.sup.+ regions 4 and deeper into the n.sup.- region 2 than the p base region 3, is a p.sup.+ well 5. In order to form an n.sup.- type channel on the p base region 3 between the n.sup.+ region 4 and the extruded portion of the n.sup.- region 2, a gate electrode 7, connected to a gate terminal G, is formed in an insulating film 6. In the contact hole formed between regions of the insulating film 6, an emitter electrode 8 is connected to the emitter terminal E and is in contact to both the p well 5 and the n.sup.+ source region 4. Connected to the p.sup.+ collector region 1 is a collector electrode 9 which is connected to a collector electrode C.
When a positive voltage is applied to the gate terminal G and the collector terminal C, and the emitter terminal E is connected to ground, the surface of the p base region 3 under the gate 6 is inverted and an n.sup.- type channel is formed by the same principles of operation as in the formation of an electron channel in a MOSFET.
As a result of the formation at the n.sup.- type channel, the n.sup.- drift region 2 is effectively connected to the ground potential, and a positive hole current is injected from the p.sup.+ collector region 1. In effect, the injection of minority carriers (positive holes) occurs in the n.sup.- drift region 2 because it is the high resistance region. Since the injection of the minority carriers satisfies the electric charge neutralizing conditions, the concentration of electrons, as the majority carriers, increases, and the resistance of the n.sup.- region decreases to a large extent, by the so called conductivity modulation effect.
FIG. 3 shows the structure of an n.sup.- type channel power MOSFET. This MOSFET is provided with an n.sup.+ region 21 as the drain region instead of the p.sup.+ collector region 1 of the IGBT of FIG. 2, and has a n.sup.- region laminated thereon. The p base region 3, n.sup.+ source region 4, and p well region 5 are formed in the n.sup.- region 22. Gate electrode 7 is connected to the gate terminal G and is positioned on a surface area 31 overlaying the n.sup.- drain region 22, the base region 3 and the source region 4 via an insulating film 6, in the same manner as is shown in FIG. 2. In FIG. 3, a source electrode 28 is connected to the source terminal S and a drain electrode 29 is connected to the drain terminal D. These connections correspond to the emitter electrode 8 and the collector electrode 9 of the IGBT shown in FIG. 2, respectively.
In the IGBT, the emitter current is represented as I.sub.e =I.sub.h +I.sub.MOS, where I.sub.h denotes the positive hole current and I.sub.MOS denotes the electron current. If the current gain of a pnp transistor 41 (FIG. 4), comprising the p base region 3, n.sup.- drift region 2, and p.sup.+ collector region 1, is represented as .alpha..sub.PNP, the positive hole current is equal to: ##EQU1## Thus, I.sub.E is equal to: ##EQU2## As a result of changes in the .alpha..sub.PNP value, the current I.sub.h changes, which effectively means that the current of the IGBT changes.
FIG. 5 shows a representative switching waveform in the case of a turn off, and it is known that there exist a first phase 51 and a second phase 52. In the first phase 51, the channel disappears and the electron current becomes zero, causing the current to decrease instantly for that extent. In the second period, current resulting from the action of the carrier remaining in the n.sup.- region the pn.sup.- p.sup.+ bipolar transistor is decreased by the recombination of carriers at the characteristic lifetime .tau. of the carrier in the open base state. Therefore, this region is determined by the injection level of the positive hole current or the carrier lifetime .tau.. Presently, techniques used to make the element operable at higher frequencies include the control of the injection level of positive hole current by the formation of a buffer n.sup.+ layer between the p.sup.+ substrate and the n.sup.- high resistance region (cf. IEEE, IEDM Technical Digest, 4. (1983) pp. 79 to 82), the control of the concentration of the p.sup.+ substrate, or the reduction of carrier lifetime .tau. by a lifetime control process, i.e., electron irradiation or heavy metal diffusion. (cf. IEEE, Trans. Electron, ED-31 (1984) pp. 1790 to 1795).
In present IGBTs, there is a further inherent problem. As shown in FIG. 4, there exists an additional parasitic npn bipolar transistor 42, comprising n.sup.+ source region 4, p base region 3, and n.sup.- drift region 2, in addition to the pnp parasitic bipolar transistor 41. These parasitic bipolar transistors respectively have the current gain .alpha..sub.NPN and .alpha..sub.PNP, and as a result, are in the pnp thyrister structure. When the sum of the respective current gains becomes equal to or greater than 1, a phenomenon in which the thyrister is in the ON state, that is, a latch up, is generated. When the latch up is generated, the IGBT loses gate control of the current, and subsequently reaches breakdown. The catastrophic failure that is, the latch up break down, is one of the important problems in the IGBT, especially when used as for inventor control applications.
In the electric power MOSFET, the source region 4, base region 3, and drain region 22 form a parasitic npn bipolar transistor 42. One reason for the activation of this parasitic transistor is the flow of a large number of carriers through the base region 3 directly under the source region 4 to the source electrode 28. This flow of carriers generates a voltage drop along the source base connecting part of the power MOSFET. When the voltage drop exceeds the threshold voltage value of about 0.7 V, this junction is biased in the forward direction causing the parasitic bipolar transistor to be turned on. This makes the control of the MOSFET current through the use of the gate signal impossible, due to the gate signal causing the MOSFET to break down. This is the so-called latch back phenomenon.
As described above and shown in FIGS. 3 and 4, the IGBT and the insulating gate type MOSFET contain respectively, a parasitic pnp thyrister and a parasitic npn transistor. These parasitic elements lead to the sudden latch up or latch back phenomenon, especially at high voltage, high electric current, and high temperature, and make the gate control function lost because of the element's destruction. In order to prevent the activation of respective parasitic transistors and hence, prevent the latch up and latch back phenomena in the conventional IGBT and insulating gate type MOSFET, such measures as the reduction of the base resistance of the p well 5 (cf. IEEE Trans. Electron. Devices, ED-32 (1985) p. 2554), the reduction of majority carries in the p base layer, and the reduction of the electric current concentrating necessary to access to the emitter and base junction parts of the element (cf. US. Pat. No. 4,809,045), have been used. Also, in recent years, by the application of a trench gate structure (cf. IEDM (1987 year International Electron Devices Meeting proceedings) p. 674) and the like, it has been reported that the latch up resistance of the IGBT has been improved to a great extent. At any rate, there exists the latching phenomenon, and when an abnormality such as, for example, a short circuit during use or a fluctuation in the wafer production process, is considered, it is natural for latch up free and latch back free devices to be desired. Thus, for example, with respect to short circuit capability, the IGBT available in today's market is by far inferior when compared with the conventional bipolar power transistor.
In addition, the above described methods for improving the latching phenomenon have the negative trade off of causing an increase in the ON voltage of the IGBT and the power MOSFET.
An object of the present invention is to solve these problems, and to provide a high performance MOS type semiconductor device in which the parasitic thyrister and parasitic transistor structures are omitted, and the latching phenomenon which has high short circuit capability is not present, but has low ON voltage independently of the short circuit capability.